Blog

Welcome to my blog. This hobby electronics project started in 2015 and went on and off for years. The first attempt was non-professional by me, a software person at that time. The idea was based on an ADI chip and was never finished. Numerous mistakes were made. There was an insufficient power budget, too many power rails, reliance on specific parts with too low of resolution and bandwidth, attempts to fabricate an enclosure before solving core functionality, ignorance of literature like Agilent Impedance Handbook, having no in-circuit debugging, using inadequate CAD tools, attempting to go lead-free in fabrication, attempting to scale fabrication too early, attempting to make the instrument a standalone with screen, etc.  

After learning a lot about firmware tools, USB, circuit design, and fabrication it became possible to restart the build with the most recent knowledge, tools, and skills. The details, schematics, and links to the GitHub source code will be published here. 

Firmware story

The task of firmware is to perform an acquisition at single given frequency. At boot (USB plug, power on reset, software reset) after initializations for all peripherals the frequency is at some default value, say 1 kHz. The magnitude of "V" and "I" outputs is 1 V peak-to-peak, the phase difference between V and I is zero degrees. Firmware will perform a delay for device under test to settle into a steady state after application of a signal. The start default delay is zero. The acquisition is a capture of 512 voltage values at the 2 analog inputs through ADC and into FIFO. 

The raw 512 data points have to represent at least 5-10 full sin cycles of test frequency at the pair of input channels.  Firmware will possibly need not to validate any choices of frequencies, magnitudes, phase offsets, delays and channel selectors. This logic should belong to PC software. The major task for firmware is to abstract the specifics of used DDS chips, ADC, FIFO depths etc. into a small set of commands and response formats, so the future changes of firmware, hardware and software will be easier to maintain.

Parts list

Schematic diagram (3 sheets) download PDF 

DDS low pass filter calculation

The low pass filter type was chosen for flatness of magnitude and phase slope. It seems that Bessel kind of filter has the best curves. Its simplicity will help to avoid surprises later when debugging the math in software. The source impedance of DDS part was taken from ADI application notes. Their reference schematics use similar filter values for impedances. The band cutoff frequency is 11 MHz to allow some nicer charting later. If the instrument will ever perform at 10 MHz, then having a few points beyond 10 MHz will help to ease the perception of capabilities having no hard set limit. Say the accuracy will be specified up to 10 MHz only. Something like this.

October 15 2022

Frequency plan, clocking tree, undersampling, aliasing, acquisition window length in presence of 50 or 60 Hz background noise, immunity of single bin Fourier to slow transients, magnitude envelope for better Fourier.

To see if the under-sampling approach can be expressed in understandable formulas to calculate 28-bit DDS frequency words the sheet calculations were done. The frequency plan derives from the known frequency of the master clock crystal oscillator, the number of samples of FIFO in a single continuous run, the number of full waves of the carrier frequency to acquire, and the practical top triggering frequency for ADC. 

There was a failed attempt to fit all acquisitions into a window equal to an integer number of 100 ms intervals. That would help with immunity to both 50 and 60 Hz AC mains interference. This feature is so far impossible. The optimistic assumption is that such immunity is important for measurement circuits involving analog DC integrators. The LCR will perform integration in the digital and software domain, so AC mains is less of an issue, which is yet to see. In theory, the single bin Fourier, aka Synchronous Phase and Magnitude Detector should be insensitive to frequencies outside the carrier.

The ADC frequency is less than 100 kHz for any carrier frequency. The ADI part can handle up to 500 kHz, however, the datasheet shows a better resolution at lower frequencies.

The under-sampling, in a few words, is the technique, when acquisition sampling is below Nyquist. This situation leads to considering so-named aliasing, the notion of the frequency bandwidth of sample-hold circuit of a particular ADC, etc. The choice of slow ADC was done deliberately, to exploit the fact that sample-hold is capable to perform up to 10MHz with a tolerable 3dB loss.

The magnitude envelope seems to be not needed. The calculations show that it is possible to always acquire an integer amount of full waves. So the Fourier output will not contain slopes around the carrier. Also, the aliasing is the major design feature and not a bug. In the case of the LCR meters in general, there is no need to consider any other frequency than the carrier one.

Controlling the phase relations across three DDSs for test signals and the ADC acquisition strobe. This is achieved with clock gating and clocking DDS, MCU, ADC, and PSU from the same clock. After steering the phase of each DDS to set value, the firmware hands over the clocking. The DDS will keep running in phase coherence indefinitely. After any set delay for DUT settling, say 100 msec, the MCU lets go FIFO RESET signal. FIFO fills up with the phase coherent data from two channels of ADC.

This manner of asynchronous control and reliance on FIFO makes firmware development easier and does not require time and clock critical elements like FPGA.

Phase resolution, steering the DDS phase, main clock handover, clock gating

TODO .. (paragraph)

TODO .. (paragraph). Transients at DUT plane, delays for asymptotic transients, single power rail opamps, DC decoupling at 10 Hz

TODO: .. (paragraph). Calculation theory, reliance on Ohm and time reference units only. Ratiometric approach with no absolute references of voltage. RF bridge kinds of LCR meters, null-metering for balancing. Two channels for null-metering. Opportunities to cancel out errors. Error budgets. 

TODO: .. (paragraph). Probe cables effects. Idea to have embedded set of standard resistors and embedded "twin" probe cable inside the enclosure for calibration. Attempt to review prior art. Note the best-in-class instrument use of same channel for I and V signal commutated to stay ratiometric. Note that they use 45 degrees stepping in demodulator of phase detector. Some remote similarity of dual slope integrator to math Fourier bin. Attempt to look at the pros and cons of solving integration on PC side instead of an analog integrator.

October 16 2022

Ready to start soldering.

October 23 2022

November 2022

Firmware is 10% done. Can communicate over USB, run self-tests with request and response in text strings up to 64 bytes. Able to use I2C and talk to IO extender chip.

Test01: microseconds counter works.

Test02: microseconds counter is accurate for milliseconds long spans.

Test03: I2C chip returns expected silicon ID value OK. Required special care about I2C protocol feature related to clock stretching. Solved with use of Atmel GPIO bitbang instead of SERCOM. Specific care about bits controlling ATSAME51 PORT peripheral to maintain ability for OUT and IN direction at the same time with no hard pull up.

Test04: I2C chip is able to change outputs with specific drive strength. Tested on LEDs OK.